(1) Field of the invention
The present invention relates to a method of fabricating the capacitors of a dynamic random access memory (DRAM) cell, and more particularly to a capacitor structure with rugged surface for high density DRAM applications.
(2) Description of the related art
A DRAM cell comprises metal-oxide-semiconductor field effect transistors (MOSFETs) and capacitors that are built in a semiconductor silicon substrate. There is an electrical contact between the source of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
In recent years, the sizes of the MOSFETs and capacitors have become continuously smaller so that the packing densities of these DRAM devices have increased considerably. For example, a number of semiconductor manufacturing companies in the world have already begun mass production of 16 M bit or even 64 M bit DRAMs. These high density DRAMs offer the advantages of longer refresh time as well as less power consumption. However, as the sizes of the capacitors become smaller, so as the capacitance values of the capacitors are decreasing, that reduces the signal to noise ratio of the DRAM circuits, causing the performance problem. The issue of maintaining or even increasing the surface area of the storage nodes or reducing the thickness of the dielectric layer is particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices.
There are two ways to deal with this problem: increasing the thickness of the bottom electrodes or increasing the surface area of the capacitors. Since increasing the thickness of the bottom electrodes is very difficult for precision lithography and etching control, increasing the capacitor surface area becomes an easier approach when the capacitor is used to fabricate 16 Mbit DRAMs and beyond. Various shapes of capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. of Hyundai Electronics (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor storage node. Another U.S. Pat. No. 5,021,357 to Taguchi et al. of Fujisu (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating fin structure capacitor electrode. U.S. Pat. No. 5,021,357 to Choi et al. of Samsung (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cylinder-shaped capacitor structure. These capacitor structures can effectively increase the capacitance values of the capacitors, however, these processes are too complicated and highly fastidious. They are difficult to be practically employed for DRAM mass-production.
The hemispherical grained silicon (HSG-Si) is a newly developed technology, which can be used to form capacitors with larger surface area. Having the features of rugged surface area, the HSG-Si becomes more and more popular to fabricate different capacitor structures. HSG-Si deposition is described in the article entitled "A New Cylindrical Capacitor Using Hemispherical Grained Silicon (HSG-Si) for 256 Mb DRAMs" by Watanabe of NEC, IDEM 92, pp. 259-263, which is fully incorporated by reference.